Tuesday, July 16, 2013: The Department of Electronics and IT (DeitY) has constitutes a technical evaluation committee to evaluate applications received under M-SIPS Scheme for assembly testing marking and packaging (ATMP) of logic microprocessor, memory, chip components, discrete semiconductors, power semiconductors, LEDs, LCD fabrication, LCD glass substrate products. The members of the Committee are as under:
1. Dr. M. J. Zarabi (former CMD, SCL Ltd.)
2. Prof. Dhrubesh Biswas, IIT Kharagpur
3. Prof. Juzer Vasi, IIT, Mumbai
4. S.K. Marwaha, Director, DeitY (Co-ordinator)
5. Vivek Sharma, ST Microelectronics
6. Jaswinder Ahuja, Vice President Cadence
DeitY may nominate other experts as necessary to the technical evaluation committee.
For further details, please contact Vandana Srivastava, additional director, DeitY (Email: [email protected])
