InCore Unveils Six-Core RISC-V Test Chip To Accelerate Design Adoption

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InCore Semiconductors has introduced a six-core RISC-V test chip that utilises the company’s proprietary generator technology to build its flexible architecture, allowing for the instantiation of various cores tailored for specific applications, such as BLDC motors and smart-card systems.

In an exclusive interview with EFY, CTO Neel Gala explained how the company developed the test chip using its two core generators, Azurite and Calcite, which can generate multiple core variations. 

“In response to customer inquiries regarding the stability of our technology, we utilised an internal test chip to automate the instantiation of four different Azureites and two Calcites, demonstrating the reliability of our generator technology. This automation streamlines the development process, essential for accelerating time-to-market for our clients,” he elaborated.

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InCore’s six-core RISC-V test chip demo at SEMICON India

The test chip has been designed with a small Arduino kit, integrating multiple security IPs and peripherals. At SEMICON India, InCore demonstrated Zephyr OS running on the chip, which is a first in the RISC-V ecosystem, said Gala. “By creating multiple cores with equivalent specifications on a single die, we allow users to switch functionalities seamlessly, providing flexibility akin to ARM’s M0, M1, and M2 cores,” he stated.

The introduction of the six-core RISC-V chip is part of InCore’s broader strategy to engage with startups under the design-linked incentive (DLI) programme, to understand market needs and support innovative projects that address emerging technology trends.

The startup partnered with a major DLI-supported company last year on energy meter products for large-scale adoption in the Indian market. “We expect to help them navigate price competition in a saturated market,” says Gala. InCore is also partnering with another startup focused on AI chips for telecommunications and 5G/6G applications. 

The DLI programme has been instrumental in providing startups access to EDA tools, via government partnerships with major vendors like Synopsys and Cadence. This financial support allows startups to focus on product development without the burden of hefty tool costs.

InCore has been actively involved in discussions to refine policies and enhance accessibility for startups, drive RISC-V adoption and support unique product development in areas like home automation, smart devices, and next-generation computing.

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Yashasvini Razdan
Yashasvini Razdan
Yashasvini Razdan is a journalist at EFY. She has the rare ability to write both on tech and business aspects of electronics, thanks to an insatiable thirst to know all about technology. Driven by curiosity, she collects hard facts and wields the power of her pen to simplify and disseminate information.

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