The 3-nanometer (nm) manufacturing node using the Gate-All-Around (GAA) transistor architecture by Samsung Electronics has begun.
This production, when matched to its 5nm process, consumes 45% less power, offers improved performance by 23%, and has a 16% smaller surface area. It incorporates a gate-all-around (GAA) transistor architecture. Larger channels are packed in gates for electricity to flow through while lowering the voltage level. In such a manner, all four sides of the channels are utilized, enabling a greater amount of drive current to pass through the gates.
The company is also working on a second-generation 3nm process node that would be better in terms of power use, performance, and surface area.
Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics, said, “Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET. We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”
