Liquid metal-based thermal solutions offer efficient cooling but face challenges like spillage and reliable thermal resistance in ultra-thin layers. Akanksha Sondhi Gaur and Nijhum Rudra from EFY delved into these issues with Dr Andy C. Mackie, Principal Engineer, Advanced Materials at Indium Corporation, uncovering key insights.
Q. Could you share insights into the recent advancements in thermal interface materials (TIM)?
A. Our Heat-Spring series of patterned metal TIMs has been widely adopted by leading manufacturers. The latest iteration is a low-pressure metallic TIM engineered for high-performance heat transfer, particularly for TIM1.5 CPUs, GPUs, and TIM2 in power modules. This version offers exceptionally low thermal resistance, supports sustainability through recyclability, and eliminates hotspots by enhancing surface contact under low pressures.
Meanwhile, the Gallitherm product line features liquid metal and liquid metal pastes (LMPs) based on gallium alloys, which remain liquid at or near room temperature. These materials deliver high bulk thermal conductivity (k) and low interfacial resistance, making them ideal for advanced electronics such as AI SiP (system-in-package) modules and power semiconductors. With module sizes now reaching up to 0.10 x 0.10 metres (10cm x 10cm) and larger designs in development, our LMPs outperform traditional TIMs by reducing interfacial resistance and maintaining controlled bond line thickness without leakage.
Our recent liquid metal TIMs apply ultra-thin layers with minimal squeeze-out, ensuring stable performance even through thermal cycling. These innovations have achieved thermal resistance below 0.005 K/W, setting a benchmark for reliability and efficiency in high-performance applications.
Q. How are emerging technologies like 5G influencing your thermal management strategies?
A. 5G base stations introduce unique challenges due to thermal cycling in power amplifiers, which now shift from high temperatures (up to 120°C and beyond) during operation to near-environmental levels during off-peak sleep modes. This fluctuation demands TIMs and solder that withstand not only constant high temperatures but also repeated thermal stresses.
Gold alloys, with their high melting points and unparalleled reliability under such conditions, are a preferred choice despite their cost. They are essential in removing heat effectively in critical 5G applications, maintaining performance and integrity through these demanding cycles.
Q. Can you explain the reliability of your products, especially for automotive?
A. Reliability is critical in automotive applications, particularly in EVs, where components must endure extreme power cycling and harsh ambient conditions. Our Durafuse HR (high-reliability) solder paste, widely adopted by leading automotive manufacturers, meets these stringent demands in applications like large ball grid arrays (BGAs).
For mobile applications, our patented Durafuse LT (low-temperature) solder paste has been embraced by a global manufacturer expanding in India. Designed for low-melting applications, it delivers exceptional drop-shock reliability, making it ideal for the Indian mobile and IoT markets. The multi-alloy system enables solder joints to form at lower temperatures without compromising strength, ensuring durable, well-wetted joints.
Q. How do you maintain consistency in manufacturing with advanced materials?
A. Manufacturing consistency is vital for advanced materials like SiP solder pastes, especially for critical sectors like automotive, where compliance with standards such as IATF 16949 is mandatory. For instance, ensuring precise jetting performance requires solder paste with stable viscosity, homogeneity, and finely tuned mixing processes.
Our close collaboration with jetting equipment manufacturers ensures full compatibility and optimal performance, meeting the high demands of automotive and consumer electronics applications. Additionally, our optimised supply chain guarantees material consistency. Top-tier semiconductor and EV manufacturers have adopted our products, a testament to their reliability and performance consistency.
Q. What are advancements in flux technology for high-reliability automotive and semiconductor applications?
A. We use a proprietary alloy that offers extremely high insulation resistance (HIR), preventing current leakage under high voltage for superior reliability. It operates within a wide temperature range of -40°C to 125°C and up to 150°C, exceeding AEC-Q100 standards for automotive applications. This durability is proven through over 1500 successful thermal cycles. We have also developed a low-temperature solder with mixed alloy technology, which is ideal for mobile devices due to its shock resistance and precision. Leading companies like Micronic use it for high-quality, precise dot jetting, under 100 microns, with high throughput.
Q. How do chipset-based systems impact the role of outsourced semiconductor assembly and test (OSAT) providers?
A. The rise of chipset-based systems has increased assembly and testing complexity for OSAT providers, who have previously embraced packaging methods like SiP, flip-chip, and 3D stacking. As fabs such as TSMC and Intel take on more ‘packaging-like’ tasks, OSATs either shift more towards these areas or move to more specialised roles like mechanical attachment and assembly for complex systems. They adapt to heterogeneous integration, manage components like processors and sensors in one package, and collaborate with foundries and design houses. Customisation for applications such as AI, 5G, and automotive, advanced materials, and sophisticated testing are now critical, alongside the need to reduce costs and speed up time-to-market. Our materials have been adopted by top-tier semiconductor and EV manufacturers, which is a testament to the reliability and consistency we can achieve.
Q. What are the challenges posed by glass substrates?
A. Glass substrates are increasingly used in advanced packaging due to their favourable properties like thermal stability and lower cost, but they are also more fragile than silicon-based substrates. Silicon-based interposers are becoming increasingly expensive, and alternatives like glass substrates and embedded interconnects are emerging. Still, there are known trade-offs between the dielectric loss properties of glass and its coefficient of thermal expansion (CTE). Managing the fragility of glass and other aspects like moisture absorption presents significant challenges for OSATs and fabs alike.
Q. What is the latest on wide band gap (WBG) power electronics?
A. Innovations in power electronics include vertical gallium nitride (GaN) transistors, which support significantly higher voltages (>650V) compared to current horizontal devices and are poised for use in lightweight onboard charging modules. The global adoption of silicon carbide (SiC) is also accelerating. However, advancements in older technologies, such as thinned silicon insulated-gate bipolar transistor (IGBT) wafers, will continue to influence the price-performance competition between WBG and silicon for the foreseeable future.
Silicon carbide stands out for enabling smaller, more efficient devices, particularly in high-voltage renewable applications like wind power. While SiC can withstand higher temperatures, its increased resistance (RDS(on)) at elevated temperatures impacts overall performance. Unlike logic and memory die areas, which are growing with advances in substrate technology, power devices are shrinking to enhance power density. Addressing these thermal challenges may require new materials and improved system-level thermal management solutions.
Q. How are you addressing thermal management challenges in power electronics?
A. Thermal management in power electronics presents challenges across multiple interfaces, including die-to-substrate, substrate-to-heat sink, and within power modules due to temperature fluctuations during power cycling. To mitigate these stresses, heat sinks are intentionally bowed by 50-100 microns (0.05mm-0.1mm) to accommodate expansion and contraction.
Our latest TIMs achieve ultra-low thermal resistance (<0.0003 K·W), optimising performance even under stress. Thin TIMs often fail under cycling, while thicker TIMs require higher bulk thermal conductivity. Our patented indium-based Heat-Spring technology combines superior thermal conductivity with structural compliance, ensuring durability and efficient heat dissipation. Materials like tin, indium, and their alloys excel in flexibility and conductivity, preventing mechanical failure. For applications requiring higher melting points and stronger solder joints, antimony-based alloys deliver exceptional performance.
Q. How do these solutions align with industry standards and customer requirements?
A. Alignment with customer needs and industry standards is at the core of our approach. We actively collaborate with standards bodies such as SEMI, AEC, and IPC to ensure our solutions meet evolving industry benchmarks. This strategic participation keeps us attuned to trends like IoT device miniaturisation, where compact, high-reliability connections must operate under harsh conditions with optimal thermal management and long lifespans.
For example, our work with JEDEC on revising the JESD94 standard addresses mission profiles and use cases for diverse electronic equipment, from mobile devices to deep-space vehicles. These collaborations ensure our solutions remain aligned with customer expectations and industry progress.
Q. What sets your solutions apart from others in the market?
A. Our competitive edge lies in innovation, proprietary technologies, and top-tier technical support, rather than focusing solely on price. Mixed-alloy solder pastes enhance thermomechanical reliability, while our InFORMS materials utilise matrix structures to maintain bond line stability during thermal cycling.
Our indium-based Heat-Spring materials, with 86W/mK thermal conductivity, maintain structural integrity under compression, minimising thermal resistance. Patented surface patterning further optimises performance at low pressures. In addition, our solder pastes employ transient liquid phase (TLP) bonding, where low-melting alloys form strong joints that solidify at higher temperatures, ensuring reliability in demanding applications like automotive and high-power electronics.
Q. How do you address specialised customer requirements for unique applications?
A. It is crucial to differentiate between one-off requests and broader industry needs. We rely on industry standards like those from the AEC for custom applications, such as specific temperature cycling or durability requirements. As a key materials supplier, we assess these demands based on our extensive industry experience and established guidelines, such as AEC-Q100. For example, our role on the AEC’s technical board in the US keeps us aligned with evolving global standards, ensuring our materials meet stringent requirements across various applications.
Q. What is India’s current role in the global semiconductor manufacturing industry?
A. India’s growing role in semiconductor manufacturing is now inevitable, especially with investments from companies like Micron and intense, focused native companies like Tata, Kaynes, and others. However, as Professor R. Tummala wisely pointed out in his book, A Vision for India to be a Global Hub for System Foundry, “there exists a gap…between academic R&D and industry’s need for manufacturing to make competitive products.” India is navigating a technology gap between traditional manufacturing processes like BGA assembly, wire bonding, and emerging advanced assembly technologies. As India strengthens its position in the semiconductor supply chain, it will need to adopt more advanced processes to remain competitive globally.
Q. What do you mean by a ‘technology gap’?
A. The technology used for some of the current manufacturing processes in India, like wire bonding, flip-chip, and 28-nanometre processes, needs improvement compared to the more advanced technologies emerging globally. These advances include sub-2 nanometre transistors, hybrid bonding, and a slew of process advances phasing out organic materials in favour of inorganic alternatives, which we call the ‘ossification’ trend.
Q. Can you explain the significance of ‘ossification’ in semiconductor processes?
A. Yes, it is quite a fitting analogy. In medical terms, ossification refers to the process where organic tissue gradually turns into bone—in more general terms, organic matter becomes inorganic. In semiconductor manufacturing, we are seeing a similar transition where inorganic compounds like metals and their oxides and nitrides replace organic materials. This shift is driven by the need to minimise the CTE mismatches and moisture sensitivity while enhancing the robustness and reliability of advanced chips, particularly as they scale down in size. The need is, therefore, for a more monolithic approach. It should be noted that this may not be the most cost-effective method, as organics are much cheaper and more flexible (both literally and figuratively).
Q. What are the implications of this transition for manufacturing in India?
A. For India as a whole, this transition is going to reshape the semiconductor assembly landscape. Processes that involve inorganic materials will become more suited to the back end of the manufacturing line, particularly for assembly tasks that used to be handled by OSAT providers. This change challenges the traditional model where wafers are processed at fabs and then sent to OSATs for final assembly. With increasing sensitivity to moisture, temperature, particle contamination, and wafers’ fragility, there is a growing argument for more of these processes to be consolidated within fabs. Thankfully, due to the visionary academic leadership team of the India design, semiconductor, packaging and system (IDSPS) team, a practical and, most importantly, actionable plan is now underway to make advanced packaging a reality in the coming years.
Q. How do you view India’s transition with Tata entering the semiconductor industry?
A. India’s entry into semiconductor manufacturing will be pivotal in bridging this gap. Companies like Tata are well-positioned to evolve quickly in response to these new demands. In the coming years, they will need to handle highly sophisticated processes such as managing glass substrates, which present their own fragility and moisture absorption challenges. There is also the matter of integrating chiplets into packaging, a technology that is becoming increasingly common in high-performance computing.
Q. How will technological changes shape India’s semiconductor landscape in the coming years?
A. India is uniquely positioned to play a crucial role in the global semiconductor supply chain. With investments in advanced manufacturing and partnerships with global semiconductor companies, India could become a leader in handling complex assembly processes that involve emerging technologies like chiplets and vertical GaN power transistors. The key will be ensuring that Indian manufacturers can close the technology gap quickly and adapt to these new inorganic materials and processes. If they can do that, they will be able to meet the growing global demand for advanced semiconductor devices.
For us, the Indian market presents a significant growth opportunity. There is unprecedented heavy government and industry investment in electronics manufacturing, and we are aligning ourselves with this growth. We currently operate a factory in Chennai, and by 2030, Indium Corporation aims to strengthen its presence in the country with an increase in manufacturing and blending facilities. While the path forward will depend on factors such as economics, global supply chain dynamics, and geopolitical developments, we are committed to supporting India’s growth and development.
Q. How do those geopolitical factors, such as China’s role in material supply, impact your strategy?
A. Geopolitical factors greatly impact our strategy. We are actively pursuing partnerships and implementing strategies to strengthen and secure the resilience of our global supply chain and to ensure the stability of critical materials supplies. More details will be shared next year.
